Manufacturing a Silicon Wafer
Growing a silicon ingot can take anywhere from one week to one month, depending on many factors, including size, quality and the specification. More than 75% of all single crystal silicon wafers are grown by the Czochralski (CZ) method. CZ ingot growth requires chunks of virgin polycrystalline silicon. These chunks are placed in a quartz crucible along with small quantities of specific Group III and Group V elements called dopants. The added dopants give the desired electrical properties for the grown ingot.
The most common dopants are boron, phosphorus, arsenic, and antimony. Depending on which dopant is used, the ingot becomes a P or N type ingot (Boron: P type; Phosphorus, Antimony, Arsenic: N type).
The materials are then heated to a temperature above the melting point of silicon, 1420-degrees Celsius. Once the polycrystalline and dopant combination has been liquefied, a single silicon crystal, the seed, is positioned on top of the melt, barely touching the surface. The seed has the same crystal orientation required in the finished ingot. To achieve doping uniformity, the seed crystal and the crucible of molten silicon are rotated in opposite directions. Once conditions for the crystal growth have been met, the seed crystal is slowly lifted out of the melt.
Growth begins with a rapid pulling of the seed crystal in order to minimize the number of crystal defects within the seed at the beginning of the growing process. The pull speed is then reduced to allow the diameter of the crystal to increase. When the desired diameter is obtained the growth conditions are stabilized to maintain the diameter. As the seed is slowly raised above the melt, the surface tension between the seed and the melt causes a thin film of the silicon to adhere to the seed and then to cool. While cooling, the atoms in the melted silicon orient themselves to the crystal structure of the seed.
Once the ingot is fully grown, it is ground to a rough size diameter a little larger than the desired diameter of the finished silicon wafer. The ingot is then given a notch or flat to indicate its orientation. Once it has passed a number of inspections, the ingot is sliced into wafers. Because of the silicon’s hardness, a diamond edge saw is used to accurately slice the silicon wafers so they are thicker than the desired specification. The diamond saw also helps to minimize damage to the wafers, thickness variation and bow and warp defects.
After the wafers have been sliced, the lapping process begins. Lapping the wafer removes saw marks and surface defects from the front and backside of the wafer. It also thins the wafer and helps to relieve stress accumulated in the wafer from the slicing process.
Once the silicon wafers are lapped, they go through an etching and cleaning process using sodium hydroxide or acetic and nitric acids to alleviate microscopic cracks and surface damage caused by lapping. A critical edge grinding procedure takes place to round the edges, drastically reducing the probability of breakage in the remaining steps of manufacturing and later when device manufacturers use the wafers. After the edges are rounded, depending on the end user’s specification, often times the edges will be polished, improving overall cleanliness and further reducing breakage up to 400%.
The final and most crucial step in the manufacturing process is polishing the wafer. This process takes place in a clean room. Clean rooms are rated and range from Class 1 to Class 10,000. The rating corresponds to the number of particles per cubic foot. For reference, these particles are not visible to the naked eye and in an uncontrolled atmosphere, such as a living room or office, the particle count would likely be 5 million per cubic foot. To help maintain this level of cleanliness, the workers must wear clean room suits that cover their body from head to toe and are designed to not collect or carry any particles. They also will stand in a vacuum that blows away any small particles that might have accumulated before entering the room.
Most prime grade silicon wafers go through 2-3 stages of polishing using progressively finer slurries or polishing compounds. The majority of the time the wafers are polished on the front side only, excluding 300 mm wafers which are double side polished. Polishing produces a mirror finish. The polished side is used for device fabrication. This surface must be free of topography, micro-cracks, scratches, and residual work damage.
The polishing process occurs in two steps. First, stock removal followed by final chemical mechanical polish (CMP). Both processes use polishing pads and polishing slurry. The stock removal process removes a very thin layer of silicon and is needed to produce a wafer surface that is damage free. The final polish doesn’t remove any material. Its sole purpose is to remove a haze from the polished surface that is produced during the stock removal process.
After polishing, the silicon wafers are processed through a final clean that uses a long series of clean baths. This process removes surface particles, trace metals and residues. Often times a backside scrub is done to remove even the smallest particles.
Once the wafers complete the final cleaning step, they are sorted to specification and inspected under high intensity lights or laser-scanning systems in order to detect unwanted particles or other defects. All wafers that meet specification are packaged in cassettes and sealed with tape. Then they are placed in a vacuum-sealed plastic bag and an air-tight foil outer bag to assure that no particles or moisture enter the cassette upon leaving the clean room.
The Polishing Corporation of America is proud to introduce you to the raw material process we use to create our silicon wafers. Silicon is a blue-gray, brittle, chemical element in the same group as Carbon. At 27.8%, it is second only to Oxygen, as the most common element on the surface of the earth.